G.C.E. A/L ICT: Logic Circuits & Memory Elements
Complete Guide to Adders and Flip-Flops (Sri Lankan Syllabus)
1. Adder Logic Circuits
In the Central Processing Unit (CPU), the Arithmetic Logic Unit (ALU) is responsible for performing mathematical calculations. The fundamental building block for addition in digital electronics is the Adder.
- Purpose: Used to add binary numbers.
- Types: There are 2 main types: Half Adder and Full Adder.
- Main Difference: A Half Adder cannot handle a Carry-In from a previous addition, whereas a Full Adder can.
2. The Half Adder
A Half Adder is a combinational logic circuit that adds two single binary digits. It produces two outputs: the Sum (S) and the Carry-out (Cout).
Block Diagram
Truth Table
| Input A | Input B | Sum (S) | Carry Out (Cout) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Logic Expressions & Circuit
By observing the Truth Table, we can derive the Boolean expressions:
Cout = A · B (AND Gate)
Circuit Construction: To build a Half Adder, you need exactly 1 XOR Gate and 1 AND Gate.
3. The Full Adder
A Full Adder overcomes the limitation of the Half Adder. It adds three inputs: Two operands (A, B) and a Carry-In (Cin) from a previous stage. This allows us to add multi-bit numbers (like 101 + 011).
Example Calculation: 101 + 011
When adding binary numbers, we start from the Least Significant Bit (LSB). If a column generates a carry, it becomes the Cin for the next column.
+ 0 1 1 (Operand B)
-------
1 0 0 0 (Result)
To perform this, we need Full Adders for the middle and final bits to handle the Carry In.
Block Diagram
Truth Table
| A | B | Cin | SUM | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Boolean Expressions (A/L Exam Focus)
Step 1: Write expression where SUM is 1 (Minterms)
Step 2: Write expression where Cout is 1 (Minterms)
Step-by-Step Simplification (For Cout)
In A/L ICT, you may be asked to simplify this using Boolean Algebra laws.
- Original: $A'BC_{in} + AB'C_{in} + ABC_{in}' + ABC_{in}$
- Group terms: We can replicate $ABC_{in}$ (Idempotent Law: $X + X = X$) to group with others.
$= (A'BC_{in} + ABC_{in}) + (AB'C_{in} + ABC_{in}) + (ABC_{in}' + ABC_{in})$ - Factorize:
$= BC_{in}(A' + A) + AC_{in}(B' + B) + AB(C_{in}' + C_{in})$ - Apply Inverse Law ($X + X' = 1$):
$= BC_{in}(1) + AC_{in}(1) + AB(1)$ - Final Simplified Expression:
Note: For SUM, the simplification results in the XOR relationship: $SUM = A \oplus B \oplus C_{in}$
4. Flip-Flops (Memory Elements)
Unlike Adders (Combinational Logic), Flip-Flops are Sequential Logic circuits. They have memory.
- Function: Used to store a single bit (0 or 1) of data.
- Usage: Used to build Registers, RAM, and Counters inside the CPU.
- Clock: Most Flip-Flops change state only on the edge of a Clock signal (synchronous).
Type 1: SR Flip-Flop (Set-Reset)
| S (Set) | R (Reset) | Q (Next State) | Action |
|---|---|---|---|
| 0 | 0 | Q (No Change) | Memory |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Invalid | Forbidden |
Type 2: D Flip-Flop (Data/Delay)
The D Flip-Flop solves the "Invalid" state problem of the SR Flip-Flop. It is the most common type used for data storage.
| D (Data) | CLK (Edge) | Q (Next State) |
|---|---|---|
| 0 | ↑ | 0 |
| 1 | ↑ | 1 |
Logic: Whatever value is at Input D, it appears at Output Q when the Clock pulse arrives.
5. A/L ICT Practice Questions
Q1: Which logic gates are required to construct a Half Adder?
Q2: In a Full Adder, if A=1, B=1, and Cin=0, what are the Sum and Carry Out?
Q3: What is the main disadvantage of an SR Flip-Flop when S=1 and R=1?
Prepared based on Sri Lankan G.C.E. Advanced Level ICT Syllabus.
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